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analog devices fax-on-demand hotline - page 28 analog lilli devices i features ad7341 - transmit (reconstruction) filter for 14-bit dac (ad7840) programmable attenuation (odb to -38db) ad7371 - receive filter for 14-bit adc (ad7871) programmable gain (ods to 24db) 7odb stopband attenuation 75db in-band signal-to-noise ratio better than - 75db total harmonic distortion ccitt v.32 and v.33 compatible small. 0.3". 24-pin plastic package and 28-pin plce general description the ad7341 and ad7371 are reconstruction and antialiasing fllters designed for use in high speed voiceband modems with speeds up to 14.4 kbitslsec) in accordance with ccitt v.32 and v.33 recommendations. these hlters, along with the ad7840 dac) the ad7871 adc and a digital signal processor (dsp) can be used to implement a complete modern. the ad7341 is the transmit or reconstruction ftlter. it imple- ments the filter function using a seventh order low pass switched capacitor filter and a second order low pass continuous time filter. the cutoff frequency is 305khz. the ad7371 is the receive filter. it is a high order bandpass fllter with a lower cutoff frequency of 180hz and an upper cutoff frequency of 3.5khz. the ftlter function is implemented using a second order low pass continuous time filter, a fourth order high pass switched capacitor filter and a seventh order low pass switched capacitor filter. rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. lc2mos voiceband reconstruction and antialiasing filter set ad7341/ad7371 i functional block diagrams opo op1 v" v~. rxin ad7341 s'lncoijt { j 01'0 op1 vco va. rxin svncout (3 ad7371 oso os; os2 one technology way, p,o. box 9106, norwood, ma 02062-9106 tel: 617/329-4700 fax: 617/326-8703 twx; 710/394-6577 west coast central atlantic 714/641-9391 214/231-5094 215/643-7790 obsolete
analog devices fax-on-dehand hotline - page 29 ad7341/ad7371-specifications transmit fi - ' jer 1 (vdd = vee = 5v ::f: 5%; vss = -5v ::f: 5%; agnd = dgnd = ov; clkin = 288khz (mis ratio = 40/60 to l 60/40. ta = +25dc. attenuator set at odb, unless otherwise stated,) signal-to-noise ratio stopband rejection differential group delay output characteristics output voltage offset: voltage attenuation range relative accuracr' 4 output resistance logic inputs wr, db2-db7, dpo, dpl, ds(}-ds2, syncin, clkin vinh, input high voltage vinl' input low voltage iinh' input current cjn, input capacitance clkin divider range (nl)5 logic outputs syncour divider range (n2) frequency pulse width voh' output high voltage vol' output low voltage power supplies vdd vec vss idd + ice iss power dissipation 72 75 70 70 350 db min db typ db typ db mm flstyp ; attenuator 0:5fs3.5khz snr includes noise and harmonics attenuator set at - 3odb, o:5f:53.5khz f~6.lkhz 0:5fs3.3khz and referenced to the absolute group delay at 1 khz rl = 3kfl, cl = loopf determined by db2-db7, see table iii clkin can be set to 288khz, 576khz, 864khz or 1.1 52mhz. ni is set by dpo, dpl. n2 is set by ds(}-ds2. isource = 4oofla is1nk =-- 1.6ma notes . ioperating temperature ranges as follows: j versions: 0 to + 70.c. zspedfied fur an input frequency of 288khz. this is internally divided by 5 to produce a switched capacitor filter frequency of 57. 6khz. for input &equencies lower than 288khz, the filter response is shifted down by the ratio of this input frequency to 288khz. 'measured using a :r3v, 1khz sine wave. 'measured over the full attenuation range. ~required to derive internal frequency of 288khz from clkin. 6detennined by data transmission rate. spedfications subj~t to change without notice. :!:3 :t70 0 to -38 :!:o.l 0.2 vmax mv max db dbtyp n typ rev. a -2- .-..--. -- ad734ljn parameter ad7341jp units test conditions/comments input characteristics input signal range :t3 vmax input impedance 100 mn typ filter characteristicsz, 3 , clkin frequency i 288 khz nl = 1 (i.e., dpo= 1, dpl =0) cutoff frequency 3.5 khz o.ldb down from the lowest point in the passband second harmonic -80 db typ third and higher harmonics -80 db typ passband ripple 0.4 db max o:5fs3.3khz passband gain error :to.5 db max deviation from nominal setting on programmable 2.0 vmin 0.8 vmax 10 i-lamax 10 pf max 1 to 4 - i to 8 fclkin/(nix5xn2) khz lifa.ktn fls 2.4 vmm 0.4 vmax 4.75/5.25 v min/v roax 4.7515.25 v minn max -4.751-5.25 v minn max 25 ma max 25 ida max 265 row max obsolete
analog devices fax-on-demand hotline - page 30 ad7341/ad7371 receive fi ' o jer ' (voii = vee = 5v :t: 5%; vss = -5v :!:: 5%; agnd = dgnd = ov; clkin = 288khz mis ratio = 40/60 to l 60/40. ta = +25c. pga set at odd, unless otherwise stated.) notes 'operating temperature ranges as follows: j versions: '0 to +70'c. 'specified for an input frequency of 288khz. this is inrernajly divided by 5 to produce a swirched capacitor tjltc:r frequency of 57.6khz. for input frequencies lower than 288khz, the filter response is shifted down by the ratio of this input frequency to 288khz. 'measured using a :t3v, 1khz sine wave. 'measured over the full attenuation range. 'required to derive a switched capacimr filter frequency of 288khz from clkin. 'determined by dara transmission rate. specifications subject to change without notice. rev. a -3- ,..., ad7371jn parameter ad7371jp units test conditions/comments " input characteristics input signal range ::':3 v max input impedance 10 kd typ filter characteristics2, 3 "" , . clkin frequency 288 khz ni=! (i.e., dpo=i, dpl=o) lower cutoff frequency 180 hz o.ldb down from the lowest point in the passband upper cutoff frequency 3.5 khz o.ldb down from the lowest point in the passband second harmonic 80 db typ third and higher harmonics -80 db typ passband ripple 0.4 db max 200hzsf:-s3.3khz passband gain error :to.s db max deviation from nominal setnng on pga signal-to-noise ratio 72 db min 180hz:-sf:-s3.5khz 75 db typ 60 db typ input signal level of -24db; pga gain set at +24db stopband rejection 66 db min f6.1khz 40 db typ f60khz differential group delay 360 fls ryp soohzsfs3.3khz and referenced to the absolute group delay at 1khz -".'..", output characteristics output voltage :t3 vmax ri,. = 3k!1, cl. = 100pf offset voltage ::':70 mv max gain range 0 to +24 db determined by dbo-db7, see table vi relative accuracy3, 4 :to.1 db typ output resistance 0.2 !1 typ non logic inputs wr, dbo-db7, dpo, dpl, i dso-ds2, syncin, clkin ! vinh' input high voltage 2.0 vmin i vinl.> input low voltage 0.8 vmax linn, input current 10 flamax i i cin' input capacitance 10 pf max i clkin can be set to 288khz, 576khz, 864khz or clkin divider range (ni)s 1 to 4 i 1.152mhz. nl is set by dpo, dp1. i logic outputs syncout -- --- divider range (n2) 1 to 8 i n2 is set by dso-ds2. frequency fclkin/eni xsxn2) khz ; pulse width l/fclkin fls i v on, output high voltage 2.4 v min ! isource=400fla vol> output low voltage 0.4 vmax ' isink = 1.6ma power supplies mm'.m- vdd 4.75/5.25 v miniv rnax v c.c 4.75/5.25 v miniv max vss -4.75/-5.25 v minn max inn + ice 25 ma max is5 25 ma max power dissipation 265 mw max obsolete
analog devices fax-on-demand hotline - pag!! 31 ad7341/ad7371 timing characteristics1 (vdd = vee = +5v %5%. vss = -5v %5%) note 'timing specifications are sample tested at +2s.c to ensure compliance. all input control signals are specified with tr = t,,= lons (10% to 90% of +sv) and timed from a voltage level of + 1.6v. specifications subject to change without notice. absolute maximum ratings. vootoagnd :..-o.3vto+7v vcctodgnd o.3vto+7v vddtovcc o.6vto+o.6v vsstodgnd +o.3vto-7v agndtodgnd o.3vtovcc rxin, txin to agnd vss -o.3v to vdd + o.3v rxout, txout to agndt ... vss -o.3v to vdd + o.3v digital input voltage to dgnd . . . . . . -o.3v to v cc + o.3v power dissipation (any package) to +75c ""'" looomw operating temperature range jversions oto+70c 1 a. 1 i 080..087 :/,///////.j( : 10" i .;--=.: 5 v :~//////~ ov i i i i i i .. i r 10. data vauo wr 1 i a. 1 '\. 5v ov t- notes ,. all input signal rise and fall times measured from 10% 10 90% of +5v 1'~t1~20~.. 2. timing measurement reference level is iv," . v~112 figure 1. ad7341/ad7371 timing diagram storage temperature range. . . . . . . . . . . -65c to + 150c lead temperature (soldering, iosecs) +300c note 'rxout, txout may be shorted to agnd, dgnd, vdd, vcc> vss provided that the power dissipation of the package is not exceeded. *stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indi- cated in the operational sections of this specification is not implied. expo- sure to absolute maximum rating conditions for extended periods of time may affect device reliability. only one absolute maximum rating may be applied at anyone time. caution esd (electrostatic discharge) sensitive device. the digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy electro- static fields. unused devices must be stored in conductive foam or shunts. the protective foam should be discharged to the destination socket before devices are removed. ordering guide *n = plastic dip; p = plastic leaded chip carrier (plcc). -4- rev. a limit at parameter ta = +2s0c umts comments twr 80 ns min write pulse width tds 60 ns min data setup time tdh 20 ns min data hold time tsyncjn 80 ns min syncin pulse width i temperature package model function range option* ; ad734ljn transmit filter doc to +700e n-24 ad734ljp transmit filter ooe to + 70ce i p-28a ad737ljn receive filter doc to +70ce n-24 ad7371jp receive filter doe to + 70oe p-28a obsolete
analog devices fax-on-demand hotline - page 3c ad7341/ad7371 dip pin configurations plcc txout 11 i . 241 txln al)7;mi i)ip top view i-""""i ad7371 ofp top view in", to "".1 c'"in 112 cuin 11> he ~ no connect nc . no connct terminology cutoff frequency the filter cutoff frequency is the point in the response where the amplitude begins to fall off. for the ad7341 and ad7371 it is defined as o. idb down from the lowest point in the passband. the ad7341 low pass filter has one cut off frequency at 305khz while the ad7371 band pass filter has a lower cutoff frequency of 180hz and an upper cutoff frequency of 3.5khz. signal-to-noise ratio (snr) signal-to-noise ratio (snr) is the measured signal to noise at the output of the mter. the signal is the rms magnitude of the fun- damental. noise is the rids sum of all non fundamental signals (including harmonics) up to 305khz. second harmonic second harmonic is the ratio of the second harmonic amplitude to the fundamental amplitude> expressed in dbs. third and higher harmonics this is the amplitude ratio of the rms sum of the third and higher harmonics to the fundamental, expressed in dbs. total harmonic distortion (thd) is the rids sum of the second har- monic and the third and higher harmonics. passband ripple this is the ripple in the passband section of the frequency re- sponse and is expressed in dbs. for the ad734i,- it is measured in the band 0 to 33khz, and for the ad7371 it is measured in the band 200hz to 303khz. passband gain error passband gain error is the deviation of the actual passbar.d level from the ideal passband level. for the ad7341, ;c is measured with the attenuation set to odb (db2-db7 = i); for the ad7371, it is measured with the gain set to odb (dbg-db7 = 1). rev. a ~ 5 q z . 0 ~ z >- . " " '" i u .. :> .. z .. :> '" i z ~ ~ !! >- : >< " >< i " '" :> '" z .. :> '" 6 0 0 052 is 2slnc 0$215 ,,' "so ad7371 plcc top v1ew (not ,. 5<0'.' ad7341 plcc top view (no' '" ""'i., s""",1i i " ..10.. ""'cin 111 "lobs !:..i~~~i!!jl2!.j1.!! ~~3~1~~~ " nc ~ no connect stopband rejection . this is the magnitude of the stopband response relative to the passband magnitude. the stopband is specified for frequencies greater than 6.1 khz. differential group delay absolute group delay is the rate of change of phase versus fre- quency, do/df. for the ad7341 and ad7371, differential group delay is the absolute group delay in a specified band relative to the absolme group delay at 1khz. the specified band for (he ad7341 is 0 to 3.3khz and for the ad7371 it is 500hz to 33khz. offset voltage this is the amount of offset introduced into the input signal by the filter. for the ad7341 it is measured with the attenuation set at odb, and for the ad7371 it is measured with the gain set at ode. attenuation range for the ad7341, this is the amount by which the output can be attenuated, using the digital inputs db7-db2. table i gives a selection of attenuations for various values of digital input. gain range for the ad7371, this is the amount by which the input can be amplified, using the digital inputs db7-dbo. table vi gives gain versus digital input code. relative accuracy this is a measure of the accuracy with which either the ad7341 attenuation or the ad7371 gain can be programmed, having allowed for the passband gain error. it is expressed in dbs' rela- tive to attenuation or gain setting with a digital input code of all 1 s. -5- obsolete
analog .devices fax-on-demand hotline - page 33 ad7341/ad7371 typical performance curves (v on =vcc = +5v. vss= -5v, fcuon = 288khz, fa = +25c unless othelwise stated) 0 -10 .-20 -30 !iii , -40 z x ... -50 ;:: :;, ~ -60 ... ...70 8<> -90 10 100 ,. frequencv - h. figure 2. ad7341 amplitude response -90 18<> 135 90 i 45 f 4;' 0 ~ -45 f -135 -186 500 frequencv .. iiz figure 5. ad7371 phase response ;. 0 -100 ..zoo >- -300 ~ w '" ~ -400 0 '" " -sod -.- -700 150 1> 2> meauency.. hz 3. figure 8. ad7371 group delay 101< 10k .. >0 -20 -10 '" '" -40 z ;<"50 '" ;:: ~ -60 >< '" -70 ...80 -90 100 ,. frequencv - hz 180 13$ 90 545 ~ '7 0 ~ -45 '" .. -90 -135 -180 0 3.3. figure 3. ad7371 amplitude response '" ... j w -0.1 -' .. .. i: frequency - h. figure 4. ad7341 phase response -500 3.3. -0.2 sod frequency - hz ,,100 ..200 ~ , >- -300 3.5> figure 6. passband ripple in the ad7341/ad7371 80 3.5. ,. 2. frequency - hz figure 7. ad7341 group delay 80 70 .;! ... j 75 "" z '" 10 20 30 40 50 temperature - 'c 60 01 ':' 75 a: z '" 70 20 30 40 50 temperature - analog devices fax-on-demand hotline - page 3~ ad7341/ad1371 pin i 2 3 mnemonic txout vss syncout ad7341 dip pin function description description signal output pin from filter. negative supply pin for the device. this is -5v :t 5%. this output pulse is derived from the scf (switched capacitor filter) clock and can be used in system synchronization. the pulse frequency is fsyncout = fclkin / (n1 x5xn2), where fclkin is the input frequency at clkin, n1 is the value loaded to the input programmable divider and n2 is the value loaded to the output programmable divider. ni is set by dpo and dp1 (see table ii). n2 is set by dso, dsi and ds2 and varies from i to 8. table i shows the typical syncout frequencies which can be set when fclkin is 288khz and nl is i. unlatched digital input which is used to set syncout frequency. see table i. unlatched digital input which is used to set syncout frequency. see table i. unlatched digital input which is used to set syncout frequency. see table 1. ground point for on chip digital circuitry. positive supply pin for the on chip digital circuitry. this is + sv :t 5%. this asynchronous digital input resets the internal clock circuitry from which syncout is derived. this allows syncout to be synchronized to an external signal. unlatched digital input pin which is used to set divide ratio on tbe clkin input. see table ii. unlatched digital input pin which is used to set divide ratio on the clkin input. see table ii. clock input for the device. this is internally divided to produce the scf clock. active low digital input. data for the on chip programmable attenuation is loaded to the input latch when this signal goes low and is latched when it goes high. six-bit data bus which sets the attenuation level on the output. see table iii. no connect. no connect. ground point for the on-chip analog circuitry. positive supply pin for the on-chip analog circuitry. this is +5v :to 5%. filter input. table i. setting syncout frequency using os2, os?, dso rev. a table ii. setting clkin divide ratio using dp1, dpo clkin divide ratio. ni dpi 0 0 i i dpo 0 i 0 i 4 i 2 3 table iii. output attenuation vs. digitallnpur code -7- 4 ds2 5 dsi 6 dso 7 dgnd 8 vcc 9 syncin 10 dpi 11 dpo 12 clkin 13 wr 14-19 db7-db2 20 nc 21 nc 22 agnd 23 vdd 24 txin sync-out ds2 dsi dso frequency 0 0 0 7.2khz 0 0 1 57.6khz 0 1 0 28.8khz 0 1 1 19.2khz i 0 0 1404khz i 0 i 11.52khz 1 1 0 9.6khz 1 i i 8.22khz attenuation db7 db6 db5 db4 db3 db2 db 1 1 i 1 i 1 0 0 i i i 1 1 -6 0 0 1 1 i i -12 0 0 0 1 1 1 -18 0 0 0 0 1 i -24 0 0 0 0 0 i -30 0 0 0 0 0 0 -38 obsolete
analog devices fax-on-dehand hotline ad7341/ad7371 - page 35 ad7371 dip pin function description description signal output pin from mtcr. negative supply pin for the device. this is -5v j: 5%. this output pulse is derived from the scf (switched capacitor filter) clock and can be used in system synchronization. the pulse frequency is fsyncout = fci-kin / (nl x5xn2), where fclkin is the input frequency at clkin, nl is the value loaded to the input programmable divider and n2 is the value loaded to the output programmable divider. ni is set by dpo and dpl (see table v). n2 is set by dso, dsl and ds2 and varies from i to 8. table iv shows the typical syncout frequencies which can be set when fclkin is 288khz and ni is i. unlatched digital input which is used to set syncout frequency. see table iv. unlatched digital input which is used to set syncout frequency. see table iv. unlatched digital input which is used to set syncout frequency. see table iv. ground point for on chip digital circuitry. positive supply pin for the on chip digital circuitry. this is +5v :!: 5%. this digital input resets the internal clock circuitry from which syncout is derived. this allows syncout to be synchronized to an external signal. unlatched digital input pin which is used to set divide ratio on the clkin input. see table v. unlatched digital input pin which is used to set divide ratio on the clkin input. see table v. clock input for tbe device. this is internally divided to produce the scf clock. active low digital input. data for the on chip programmable gain is loaded to the input latch when this signal goes low and is latched when it goes high. eight-bit data bus which sets the gain level on the input. see table vi. ground point for the on-chip analog circuitry. positive supply pin for the on-chip analog circuitry. this is +5v :t 5%. filter input. table iv. setting syncout frequency using 052, 051, oso table v. serting clkin ~ivide ratio using opt, opo dpl 0 0 1 1 clkin divide ratio, nl 4 i 2 3 dpo 0 i 0 i table vi; input gain vs. digital input code -8- rev. a pin mnemonic 1 rxout 2 vss 3 syncout 4 dsz 5 dsi 6 dso 7 dgnd 8 vcc 9 syncin 10 dpi 11 dpo 12 clkln 13 wr 14-21 db7-dbo 22 agnd 23 vdd 24 rxin syncout ds2 dsl dso frequency 0 0 0 7.2khz 0 0 i 57.6khz 0 ] 0 28.8khz 0 ] i 19.2khz i 0 0 1404khz i 0 i ii.52khz 1 i 0 9.6khz 1 1 1 8.22khz gain db7 db6 dbs db4 db3 db2 dbi dbo db 0 0 0 0 0 0 0 0 24 0 0 0 0 0 i i i 21 0 0 0 i 0 0 0 1 18 0 0 0 1 i i i 1 15 0 0 i i 0 0 i i 12 0 i 0 1 0 0 0 0 9 0 i i 1 i 0 0 0 6 1 0 1 1 0 0 0 0 3 i i i 1 i 1 i 1 0 obsolete
analog devices fax-on-demand hotline - page 36 ad7341/ad7371 circuit description ad7341 filter the ad7341 transmit filter performs the reconstruction or smoothing function for the transmit channel d/a converter. figure 11 is the block diagram for the filter and programmable attenuation section. txin single ended to differential conversion scf cloci( 2nd order lp continuous time filter differential to single ended converison programmable attenuation (0 to -38<18) txout figure 11. ad7341 filter section the transmit channel signal is applied at txin and is converted to a differential signal. it then goes to the fully differential switched capacitor low pass section. this is a seventh order el- liptical filter which gives a 3.5khz cut off frequency and stop- band attenuation of greater than 70db at frequencies above 6. 1khz. the use of the differential filter structure ensures an excellent harmonic distortion figure and also gives improved re- jection of common mode noise such as clock teedthrough in the switched capacitor switching transistors. the filter cut off fre- quency depends directly on tbe clock driving the switched ca- pacitor section and upon the capacitor matching. capacitor matching is typically better than 2% and this means that if the dock is constant, cut off frequency variation from device to de- vice will be less than 2%. since the switched capacitor filters are sampled data systems (analog data) with a sampling frequency of 57.6khz, they must be followed by a smoothing filter to remove aliased components due to this dock. this smoothing filter is a second order low pass continuous time section. the differential rev. a outputs of the two smoothing filters are then recombined to a single ended signal. the level of scf clock feed through at the output is typically -65db. this can be further reduced by using a simple rc combination at the outpul (39kn and looopf re- duce the feed through to -80db). the second order filter shown in figure 22 reduces it to below -90db. after recombination of the differential signals, a programmable attenuation stage fo!- lows. the anenuator circuit diagram is shown in figure 12. it consists of an 8-bit multiplying dac with the two lsbs (db i, dbo) tied high. the transfer function is given by: 256 a 20 log 4n!3 where a is the attenuation in des and n is the 6-bit binary code loaded to the device. expressing n in terms of a gives: n = ! [ 256 ] 4 1on2o-3 082 r d87 voo vou, wr v'n 8-bit multiplying dac db7 d82 figure 12. ad7341 output attenuatar this allows the calculation of the device input code for a given output attenuation. the attenuation range is 0 to 38db and al- lows the user to adapt the output signal for different line specifi- cations. figure 13 shows how attenuation varies with input code, and table iii gives a selection of attenuations for specific codes. 40 ,j13() " i z 0 ~ 20 ;> z s 10 0 0 20 40 60 device input code in) in decimal 80 figure 13. programmable attenuation v5. input code for the ad7341 -9- ....... \ \ i \ - , f--.. "'" ... -. - -'---im m ..-.......- ! -.. i -- - obsolete
analog devices fax-on-dehand hotline - page 37 ad7341/ad7371 ad7371 filter the receive filter performs the antialiasing function for the re- ceive channel nd converter. it provides rejection of high fre- quency om-of-band signals, attenuation of low frequency noise at both 50hz and 60hz line frequencies and programmable gain for the input signal. figure 14 is the block diagram for the filter and programmable gain section. rxin wa db7 duo singl!: ended to differential coni/ersion scf clock 2nd order lp contlmjous time filter 2nd order lp continuous 11me filter 4th orde1i hp switched capacitor filter 4th order hp switched capacitor fr.ter differential to single ended coni/erfson rxout figure 14. ad7371 filter section the input signal is applied at rxin and passes through the programmable gain stage. figure is shows the circuit diagram for this. it consists of an 8-bit multiplying dac and resistor combination in the feedback loop of an operational amplifier. the transfer function is given by: 272.2 g = 20 log n+ 17.2 g is the gain in dbs and n is the 8-bit binary code loaded to the device. varying this code between 0 and 255 gives a gain range of 24db to odb. expressing n in terms of g gives: n = 272.2 wzo - 17.2 ddo dbl dbo. 0-8it multiplying dac 15.85r r vqu' vw figure 15. ad7371 programmable gain amplifier this equation can be used to calculate the code, n, needed to give the desired gain, g. figure 16 is a graph of gain versus in. put code, and table vi gives a selection of gains for specific codes. 30 20 .ii .. i z :{ '" 10 0 0 100 200 device input code ini in decimal 300 figure 16. programmable gain vs. input code for the ad7371 after the pga stage, the receive signal is converted to a fully differential signal before going to the differential mters. the first differential filter is a second order continuous time section. this is necessary to provide antialiasing for the sampling switched capacitor f1lter. the continuous time filter eliminates any high frequency components from the input signal which would be aliased back into the passband of the switched capaci- tor filter and appear as noise. following the continuous time f1lter, the fourth order elliptical high pass switched capacitor section has a cutoff frequency of 180hz, and the seventh order elliptical low pass switched capacitor section has a cutoff frequency of 3.5khz. as in the reconstruction filter, the cutoff frequency variation from device to device for fixed clkin is typically less than 2%. on recombination of the differential signals, the output goes to rxout. -10- rev. a ! , i ! i ,\ ! i j \ i ..... i ' i -- '; ......... ; :! "" -.-. ...... j r- r- r- obsolete
rnrlog devices frx-on-demrnd hotline - page 38 ad7341/ad7371 scf clock and system synchroniution the clock generation circuitry for both the ad7341 and the ad7371 is identical and is shown in figure 17. for the speci- fied filter response, the switched capacitor dock must be 57.6khz. this means that clkx in figure 17 must ajways be 288khz (57.6khzx5). the input programmable divider ajlows the user the option of four clkln frequencies (288khz, 576khz, 864khz or 1152khz). the input divider can then be programmed to ensure that clkx is 288khz. 080 db1 clkin in put mog divider (1 to 4) clio( scf clk syncin sincoijt dsg os1 ds2 figure 17. ad7341/ad7371 clock generation circuitry the ad7341 and the ad7371 are always used with a dac and adc respectively. the dac and adc update and sample at a certain rate (9.6khz or 7.2khz, for example). the filters sample at 57.6khz. in order to ensure that there is no low frequency aliasing, the daciadc rate must be synchronized with the scf clock. this means the scf rate must be an integral multiple of the daciadc rate. the ad734i1ad7371 actually generates this required synchronized clock on chip. the output program- mable divider allows division of the scf clock by i to 8. the divide ratio is determined by inputs dso- ds2. the output of ad7371 y.. rxln rxout sync futse 8tncout uiih. qj( _i cutin ad7341 cuun y"", yxout txin the programmable divider goes to syncout which is then used to drive either the convst input of an adc or the ldac input of a dac. the output programmable divider also has a reset input (syncin). this is normajly tied high. when it is brought low, the counter is reset. on returning high, the counter is reactivated. by using this syncin facility, it is pos- sible to adjust the point in time at which sampling occurs while maintaining the same rate. this is useful in modem applications and is known as cycle slipping. figure 18 shows the complete timing waveforms for the ad73411ad7371. =~ jljlflfu1jlflf - - - -ljlju1jlfljljlj - -l1ulfuu1flj1j sckclk ~ rnnl ~ 1---1 ~ r 57- -.j l.j l.j l.j l.j l.j sy,.cln u ---- --'- - - - ~ - --=-.-t===. ~ - -=- ~ syncout u --- u , 1 t -[si6 x ,0> x n2) seconds figure 18. ad7347/ad7371 timing waveforms applying the ad734117371 the prime application for the ad734117371 is in the analog front end for echo-cancelling modems. here, the filters are com- bined with a high resolution dac and adc to provide the in- terface between the analog and the digital domain. the excellent noise performance of the ad7371 and the high resolution of the ad7871 (l4-bit adc) combine to allow the modem echo- cancelling loop to be implemented totally in the digital domain. this overcomes the disadvantage with lower resolution systems which need to do a digital approximation of the echo and recon- struct in analog form for an analog echo-cancelling loop. conversely, in the modem transmitter, the combination of ad7341 and high resolution dac (l4-bit ad7840) allows trans- mission of the signal with minimum impairments to the line. figure 19 shows a typical hardware interface between the analog front end chipset and the adsp-2101 in an echo-cancelling mo- dem. the adsp-2101 is the new dsp microcomputer from an- alog devices. it has program memory and data memory on chip ao7871 y.. convs'i' scu( istiiii $c.. rfs $oata dr tfs ot adsp-2101 ad7114o scu< wiiliy1ic $oata yo.. rev. a figure 79. modem analog front end and interface to adsp-2701 dsp -'1- obsolete
analog devices fax-on-demand hotline - page 39 ad7341/ad7371 and is code compatible with the adsp-zioo. it also has two serial ports. the particular configuration, shown in figure 19, uses the serial interface on both the ad7840 and ad7871 to talk to one of the adsp-21o1 serial ports. the system timing diagram is shown on figure 20. the 288khz clock drives the two filters and the adc. the syncin pulse may be used to set the absolute sampling instant. dso, dsi and ds2 on the ad7371 are programmed to give a 9.6khz syncout signal. this drives the ad7871 convst input and is thus the sam- pling rate. sclk on the ad7871 clocks out serial data on its rising edge. sstrb is the framing pulse for the serial data. within this framing pulse, a 16-bit data stream is output on the sda t a line. each data bit is valid on the falling edge of sclk. there are two leading zeros and the 14-bit conversion result appears after these. when rfs on the adsp-2101 goes low, data appearing on dr is docked into the receive shift reg- ister on each falling edge of sclk. once the 16 data bits have been received an internal interrupt is set and the processor can read the data. ~~. lju1j1iulju1f - - - -l1ulfljli1juu1f --lfu11lj1j1fuu svncln u ~ coni/st 9.6ub n- if lj - - - -1ilfuuliljljulf - -liulju1jlj1iuu =- juu1j1j1jliulim - ~ - - - ~ --- ==r- u=_-- ~ ~ l----- u-=t- u=_-- sstrb rfs soata dr wr/svnc tfs spata ot figure 20. system timing for figure 19 the circuit of figure 19 also uses the sstrb signal to frame the transmit data from the dsp . thus, when sstrb goes low, data contained in the transmit shift register of the dsp is clocked out on each rising edge of sclk. the ad7840, in turn, loads each data bit into its input register on the sclk falling edges. the dac output is updated when 16 data bits have been received. using the adsp-2101 and the chipset, the modem hardware is simplified. the number of lines required to connect the chips is much less than a parallel interface structure would need and no external glue logic is required. chipset layout figure 23 is the circuit diagram for a modem analog front end based on the analog devices chip set. the component overlay is given in figure 21, while the pcb layout is given in figures 24 and 25. the modem analog front end uses the ad7341, ad7371, ad7840 and ad7871. total channel snr perfonnance is better than 72db with a full scale input signal and unity gain on the filter chips. the 14-bit resolution of the converters gives an in- stantaneous dynamic range of 84db. if greater dynamic range is required, then the ad7371 pga can be used to give up to 24db extra. the evaluation board makes full use of the flexible interfaces on the ad7840 and the ad7871. jl is a 96-way vme bus connec- tor which carries the parallel interface for the board. this plugs directly into the connector on the evaluation board for the adsp-2100, which is another in the analog devices family of digital signal processors and is code compatible with the adsp-21o1. thus, direct interfacing between the boards is pos- sible. all the signals necessary for interfacing to other dsps are available on 11. the 9-way d-type connector, j2, carries the serial interface for the board. this allows dsps with serial ports to interface direcdy to the chipset. power supplies used to operate the board are :i: 15v analog sup- plies and a single +5v digital supply. a :i: sv analog supply is derived from the :t15v supply by using the 78lo5/79lo5 regu- lators. this supply is used for the ad7341, ad7371, ad7840 and ad7s7!. the supply grounds are tied together on the board so that there is no need to have them connected back at the sup- ply source. the analog input and output ranges are both :t iov. the analog input is attenuated by ici and associated circuitry to give the required :t 3v input range for the filter and adc. likewise, the analog output from the reconstruction filter (:t 3v) is gained up by the output amplifier (ic6) to give a :t lov omput. this out- put amplifier also contains a simple second order filter to further attenuate the switched capacitor clock noise at the output. there are three digital inputs to the board. these are clkin, adc syncin and dac syncin. clkin provides the clock for the adc and mters. the dip switches on the board have been set up to accept a nominal clock of 288khz for the filters. adc syncin and dac syncin can be used to resynchro- ruze the mters/converters with an external synchronizing signal. if this is not required, then both of these inputs should be tied high. -12- rev. a obsolete
analog devices fax-on-demand hotline - page ~0 ad7341/ad7371 0 6 3k 3k }ot.. a..ttoni 0 00 ..k i..:l-a 1..:1.7 iu:ac ~ ~~p~ck :l.euf .. .. ~~~:"' .1 be.:i. [ ~o"11c=j ~ i [ \lfn a.~ ..,ak 8 + + 8 1eu,, 0 + fj "o73,.:i. c=j ~ 18uf ~ 07871 n e.1 8,1 8.1 1s.. ..8"" 1..11 0 l,1 18" ,-r::j- 0 i.. 18 "uc::l8s+ e.1 [j~ 1 ~~t~ ~...f'- ~ i o lt fn 0 do 1a ( 1"1'101< ""..1 1-' 1auf .. 1euf +.. ~a ,.81 8..1 be,:i. 1au~00,,;b,:i. u out c=j ~.i analog devices rax-on-demand hotline - page u ad7341/ad7371 j: 1 ov '"v~'iv ... ..,.,"., 1.1.' iv ,".' ..iv "sv .'v -iiv '..' '.'.' y 1 ]i~ ... .sv .,v .'v"""" '0"'" " ...' ov ."v ,.'ov~8 -10vi .............-..... ... ic7 s... -15v ..: ""7371 * ii: "'" 5t""", lt2 "'o---o"'~ oac s.""'.. oil' ".m',' cuuf< .,.. ,..ovyto"'m mi i n01" 1. no puu.-ui' """om ",,-s""""5...omittt<>jorcliiij1y. : """""s"" ic1 'oleum allmcouft.id ""'" i.'p"'" ,".' car""""". me..,' shown. figure 23. circuit diagram for modem analog front end -14- j' ""'allee po", for '.s'.".. evil.' non ooaro ., = .. tdmacii. co "">cic- ." ."0" .n ....... .is " ... d"o'2 .," " ... ...011 .n -.. .,. """" .2. dmd' ... ..,,'" ... owoi b>2 dmd< ... 0..,' .., omd2 ..1 dmo' 827 d"d' en (co. en ",.., rev. a obsolete
analog devices fax-on-demand hotline - page ~2 ad7341/ad7371 1- -i figure 24. pcb component side layout for figure 23 rev. a -15- obsolete
analog devices fax-on-dehand hotline - page ~3 ad7341/ad7371 figure 25. pcb solder side layout for figure 23 mechanical information outline dimensions dimensions are shown in inches and (mm). 24-pin plastic dip (n-24) 28-pin plastic leaded chip carrier (p-28a) c : : : : : : : : : )~ i. 1.>21131.'" ~ ~ .."""'ii j ~..t-.- ~ o.""u., .~-::- - - - - - - - - - j - l - --r il ~ """u3! -i,.. -i to- --f . "-'"2.1,, ..."'.m ... to..., 0.""211 o:orn:ffi ... not" 1. lead no. 1 'dent"'" by dot or ndtch. 2. st1c 'eads wll 'e eit"". soldeii do..." or tin lead plated in accordance with "'l_" ii--,s. ...1 ...... -r '1.27 ..:... top view u ~ h i fc:::i:..l.. ........ ~ i n t-~" ~~ 3 - ~ :1 ' l.j u u u l..j lj i ii [t 0.'" (0."" ~ui ~- ", 50 1 ! --i -- """'i.sn .1' o.il.i3"" " 00.. ~ ~ 1 .51 1 , . "".201 i- -16- rev. a a> ~ j ~ n u ? ui ::i ~ 0 uj i- ~ ii: 0... obsolete

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